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Urgent Completion of FPGA project

$30-250 USD

Completed
Posted over 10 years ago

$30-250 USD

Paid on delivery
Urgent Completion of project. Half is done and only to add some additional segments of code. Small scale project.
Project ID: 5069836

About the project

10 proposals
Remote project
Active 10 yrs ago

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Hello, I would love to take care of your project. I have experience in VHDL description in Altera/Xinlinx FPGAs. I would need info about your projects aims and current status. If you are interested, please let me know. Best regards, Javier Oliver.
$150 USD in 4 days
5.0 (1 review)
2.6
2.6
10 freelancers are bidding on average $154 USD for this job
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Hello my friend, I have good hands on experience in VHDL, please let me know more about your project.
$222 USD in 3 days
5.0 (1 review)
3.2
3.2
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Hello! If it is realy a small scale project I can provide the solution in s few days. The bid I've placed is for aprox. 20 working hours. I can write both Verilog and VHDL. Regards, Botond
$155 USD in 3 days
4.6 (5 reviews)
3.3
3.3
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i am experienced in this filed i can help you . i am working in verilog from couple of years. please send me details.
$155 USD in 3 days
4.2 (1 review)
2.1
2.1
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Hi, I am very busy with other projects, but if it is not a complex one we could do it. Thank you, hdlveca
$155 USD in 3 days
5.0 (1 review)
1.8
1.8
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Hi What is project about? Is it Verilog, or VHDL? I've done projects with FPGA (Quartus Altera and Xilinx Spartan boards), but they were done in Verilog. If you think I can help you, please contact Cheers
$166 USD in 3 days
0.0 (0 reviews)
0.0
0.0
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5.5 Years skills of FPGA based system designing. My skills are FPGA based system designing on Verilog-HDL • Xilinx FPGA Evaluation Kits Spartan-3, Spartan 3-E, Spartan 3 PCI-E Starter Board, Virtex IV and Virtex V Evaluation Kits, Altera and Actel FPGA Kits • Xilinx ISE , Modelsim, Chipscope Pro, EDK, PlanAhead, Jungo Windrivers • Labview, Labwindows, Visual Basic, Visual C++ • PIC & 8051 Microcontrollers • FPGA Board Designing • Digital Signal Processing Designing on FPGA using System Generator • Imaging Sateelite Payload Ground Support Equipment Designing & Development • High Speed Communication Designing
$166 USD in 3 days
0.0 (0 reviews)
0.0
0.0
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hello. could you please share more detail? Such as, overview about the project, HDL language to be used, current source code to be modified/added/changed...
$100 USD in 5 days
0.0 (0 reviews)
0.0
0.0
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A proposal has not yet been provided
$155 USD in 3 days
0.0 (0 reviews)
0.0
0.0

About the client

Flag of SINGAPORE
Singapore, Singapore
5.0
3
Payment method verified
Member since Jun 16, 2013

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