VHDL code for Pipelined MIPS Processor

The pipelined processor is divided into four units: the controller, datapath, instruction memory and data memory [url removed, login to view] task in this part will be to (1) design the controller unit, (2) design the instruction memory and data memory, (3) design datapath units, (4) put all 4 units together to form the pipelined MIPS processor, and (5) work out two test programs for the processor as a whole.

It should take a maximum of 8 hours to be completed in 1 week. I will upload detailed instructions once the freelancer agrees to work on it.

Skills: Verilog / VHDL

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About the Employer:
( 0 reviews ) United States

Project ID: #4439921

4 freelancers are bidding on average $11/hour for this job


Hello! I can deliver the solution for you in 5 working days. I am available 4/hour a day. Regards, Botond

$15 USD / hour
(3 Reviews)

Hi I can help you!

$11 USD / hour
(2 Reviews)

Hi. I have implemented the same project before. Will be done in due time.

$15 USD / hour
(0 Reviews)

I have develop a Thesis about this topic, I have a complete design and working simulation running.

$4 USD / hour
(0 Reviews)