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code for floating point multiplier 32-bit

$10-30 USD

Closed
Posted about 7 years ago

$10-30 USD

Paid on delivery
code with report and explanation
Project ID: 13318087

About the project

7 proposals
Remote project
Active 7 yrs ago

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7 freelancers are bidding on average $37 USD for this job
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Dear sir I have more than 9 years experience in digital design using VHDL and verilog, please message me so that we can discuss more details
$30 USD in 1 day
5.0 (271 reviews)
7.5
7.5
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Hi, -FPGA design engineer since last 7 years -Expertise in verilog/VHDL Please find below details of the projects TSMAC Hardware acceleration(3months) The project is to develop hardware acceleration block for TSMAC IP to reduce the overhead created in software for packet creation and detetction. CSI-2 transmitter and receiver(6months) The project is to develop CSI-2 transmitter and receiver IPs according to the mipi standards eMMC Host Controller and Device controller(3months) The project is to develop eMMC host and Device controller IP according to the JEDEC standards. Mobile camera–testing(3months) The project is to develop 3D image processing algorithms on 1K sensor from PMD technologies High resolution camera(6.5months) The project is to develop 2D and 3D image processing algorithms on 100K sensor from Infineon sensor -Test project for DDR2 accesses -Development of calibration module -Development of chain control module -Development of control signal generator -Development of Generic LUT module -Development of Divider radix-2 algorithm -Development of atan calculator -Development of MCB reader state machine Color Pipeline(15months) The project is to develop 2D and 3D image processing algorithms on Aptina sensor -Development of Generic Frame Buffer pCore -Development of data compression and data packing pCore -Development of data packing pCore Video Processing Unit(13 months) -Improvement in algorithms to reduce FPGA resource utilization and decrease latency
$30 USD in 1 day
4.9 (5 reviews)
4.6
4.6
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Hi I have 12+ year of experience in Verilog and VHDL , Designing Floating Point Multiplier is trival for me , I can provide you complete project in 24 hours maximum. please let me know how to take this further , I have to use verilog/vhdl ? Thanks SK
$30 USD in 1 day
4.8 (17 reviews)
4.5
4.5
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Hi, Can we discuss the project further? I have done similar project and understood the project outline. Please give me a chance. A trial will convince you. Looking forward to work with you.
$100 USD in 1 day
0.0 (0 reviews)
0.0
0.0
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I have completed the Analog , digital and mixed vlsi course. I have also completed a project based on vhdl and simulink. My project title was "FPGA IMPLEMENTATION OF DIGITAL CONTROLLER FOR SHUNT ACTIVE POWER FILTER TO REDUCE HARMONICS AND REACTIVE POWER". I have latest version of xilinx software i.e. ISE 14.7.
$25 USD in 1 day
0.0 (0 reviews)
0.0
0.0

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India
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Member since Mar 7, 2017

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