Cancelled

grayscale image processing in Verilog

Image processing in verilog.

2 DIFFERENT IMPLEMENTATIONS IF POSSIBLE.

grayscale image processing.

Objectives :

Implement in Verilog a synchronous sequential circuit which processes the grayscale images ( with a single color channel on 8 bits) . The images have a 64x64 bytes dimension.

Requirements:

[url removed, login to view] on the image a blur filter type

[url removed, login to view] of image mirroring.

[url removed, login to view] of picture rotation (90degrees)

Blur filter which needs to be implemented is gave by the following matrix:

{0,1,0 ; 1,1,1 ; 0,1,0}

Interface to be used:

module process(

input clk, // clock

input [1:0] op, // 0 – blur type filte; 1 - mirroring; 2 - rotate

input [7:0] in_pix, // pixel value from the position [in_row,in_col] for the used image

output [5:0] in_row, in_col, // selects one row and one column from the image

output [5:0] out_row, out_col, //selects one row and one column from the resulting image

output out_we, // activates writing for the resulting image (write enable)

output [7:0] out_pix,

output done // sends a done signal when image processing is complete

);

This module will also interract with the image module, which has the following interface :

module image(

input clk, // clock

input[5:0] row, //

input[5:0] col, //

input we, // write enable (activates writing)

input[7:0] in, // value of the pixel which will be written on the current position

output[7:0] out // value of the pixel which will be read from the current position

);

In the attachment you can download the interfaces.

Skills: Verilog / VHDL

See more: image processing verilog, writing image, vhdl and verilog, verilog vhdl, pixel and type, image processing, filte, implement image, rotation module, write matrix, vhdl image processing, verilog write, verilog code video image processing, output channel circuit, image verilog, implementation image processing vhdl, pixel implementation, image steganography implemented fpga using verilog, clock interface, gui interface image design, verilog image, implement image processing, vhdl clock, image pixel, interface matrix

About the Employer:
( 0 reviews ) Bucharest, Romania

Project ID: #5187843

9 freelancers are bidding on average $405 for this job

ahmedmohamed85

Dear sir, I have more than 5 years experience in digital design and digital image processing using verilog for fpga please check my profile

$25 USD in 3 days
(53 Reviews)
6.3
Quadrupole

I have an experience in Verilog programming. I can do this project. .

$25 USD in 3 days
(2 Reviews)
2.9
adrianacd

I'm the best for this task...I can do not 2, but 200 different implementations! Also, since I am the one grading them, I will make sure to make them to trick MOSS :P.

$2222 USD in 1 day
(0 Reviews)
0.0
silviastegaru

If you pick me you won't be disappointed. I have the skills required to deliver the implementations requested and - seeing that I wrote the specifications for this assignment - you can be sure that I will take care to More

$1234 USD in 1 day
(0 Reviews)
0.0
dandragomir1337

Dear Sir and Madam, I am quite knowledgeable of the Verilog language seeing as I am teaching it for some years. You should choose me not only because of this, but also because I am very familiar with the tester used More

$25 USD in 3 days
(0 Reviews)
0.0
optimuslogicin

Hi, OptimusLogic Systems specializes in designing and developing semiconductor IP for different domains and peripheral interfaces. Our deep domain knowledge in AMBA based SoC architecture and peripheral interconnects More

$35 USD in 10 days
(0 Reviews)
0.0
PrinceJion

i have experience in this field. i implemented h.264 previously I can help you please send me details.

$25 USD in 3 days
(0 Reviews)
1.7
ashan8k

Hey I'm a final year undergraduate of Electronic and Telecommunication Engineering. I'm and Expert in verilog. I'm pretty sure I can help you Thank you

$30 USD in 10 days
(0 Reviews)
0.0
chaicko

La propuesta todavía no ha sido proveída

$20 USD in 7 days
(0 Reviews)
0.0