Implement [url removed, login to view] b/g on FPGA using simulink and Xilinx system generator

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I need to implement [url removed, login to view] b/g in simulink using Xilinx blocksets and then by using Xilinx system generator translate it into verilog and implement the design on FPGA kit (possibly Virtex 6). I need complete design in working condition. If someone can help me please reply!!

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