Code translate

1. Translate sha256.c into Verilog HDL code. 2. Your Verilog implementation should perform the exact functionality as defined in sha256.c. 3. In the 2nd milestone, we only require your code to perform correctly in logic. There is no requirement of performance and area optimization. 4. We will discuss more details in tomorrow's lecture. 5. Your delivery should consists of a) All Verilog source codes. b) The logic diagram of your design, where how each module communicates with each other should be shown. c) Your logic simulation results: numerical results and waveforms.