Using a FreeRTOS and lwIP (TCP/IP) on Xilinx ZynQ SoC.
Tool is Vivado 16.2 (SDK).
At Ethernet interface (PS of ZynQ FPGA), mixed traffic is to be differentiated based on pre-defined IP and Ports and IP packets are to be routed to respective application.
Rest all traffic (RAW Ethernet Frames) to be passed on to PL part (FPGA). This can be done by keeping Ethernet packets in DDR. And then AXI interface shall transfer the packets to into FIFO in PL. DMA engine to be used for burst transfer (AXI-4 Memoery Mapped)
Same is required in the reverse direction i.e Tx and Rx.
Besides, we are open for other TCP/IP stack as well.