Write a software simulator of an invalidate snoopy cache coherence protocol for a centralized shared memory multiprocessor with the following features:
1. 4 CPU nodes, each with private L1 data cache.
2. Cache organization: 64KBytes total capacity, 2-way set associative, 64-byte block size, 32-bit address space, uses MSI invalidate protocol described in class lecture.
3. Do not model data. Only address/tag and coherency state and bus transaction type.
4. Use OpenMP to develop your code.
5. Use one OpenMP thread for each CPU cache.
6. You do not need to model the DRAM since you are not modeling data, but only addresses and cache coherence state.
7. Simulator processes one miss at a time from start until completion.
8. Use a parallel for with an induction variable clk_count that increments on every loop iteration from a value of 1 until some very large value max_simulation_clk, large enough to complete processing all the input stimulus files posted with this assignment n Moodle.
9. Use a shared data object to represent centralized bus state. Bus state changes every clock, based on simulated cache misses and resulting cache coherent bus transactions.
10. Use a decentralized round robin priority/arbitration scheme to determine which cache can drive the bus (i.e., which cache can write the bus shared object on any given clock). Decentralized means every cpu observes its own request and requests from other cpus that want to drive the bus. They all determine in parallel the highest priority cpu that is making a request and that cpu wins priority to drive the bus. When a cpu wins the bus, it's priority is reduced to be the lowest priority cpu in the next arbitration cycle.
11. Use a synchronization barrier to make sure that every thread/cpu has already computed and driven it's request before all cpus proceed to compute the winner and the winner drives the bus.
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