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16-bit carry-ripple mirror Adder implementation in Cadence simulator

Implement the mirror adder shown in Figure 1 in 18-nm FinFET GPDK. Make sure to

properly size the FinFETs.

a. Simulate the mirror adder to determine delays from inputs to the sum and carry

out.

b. Characterize power dissipation for the fastest data rate this adder can handle.

2) Using the adder implemented in part (1) implement a 16-bit carry-ripple adder. Simulate

your 16-bit carry-ripple adder and determine the following:

a. What input data combination will result in the worst-case delay.

b. Worst-case delay through the 16-bit carry-ripple adder

c. Power dissipation for the fastest data rate 16-bit carry-ripple adder can handle.

Write a project report to present your results.

a. Make sure your report is readable with clear figures and tables.

b. Perform hand analysis

c. Compare your hand calculations with the simulation results

Skills: Electrical Engineering, Verilog / VHDL, Engineering, Electronics, Matlab and Mathematica

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