Many MOSFET application tutorials provided the solution on how to derive the KVL equation during MOSFET turned on and off process and considered the parasitic component based on resistive load cases as attached files.
I have a question about how to derive the KVL equation for the MOSFET model by considering the parasitic capacitance and gate charge process to determine the approximate rising time and falling time in an inductive load case as the attached figure (question).
I need to know how to derive the equation step by step on hand calculation. The derivation must be correct and understandable to estimate the Td(on), T rising, Td(off) and falling time.
For more information will be discussed in details.
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Hi, I am an electrical engineer with more than 10 years of experience with the engineering projects. I would like to discuss the project with you if you are interested. Thanks.
Greetings. I have a similar written work, but due to my current occupations I can do this calmly, that's why I need approximately two days, establishing a maximum of four days to complete it.