I need system verilog expert who understand concept of verification, assertions and other basic concepts..
- Logic Design and Verification
- System Verilog
- TCL/Perl or scripting
- C/C++ programming is a plus
You should have access to necessary tools like mentor graphic or anything else.
More project details will be given to candidate with proper bid and message. Please let me know about your work experience / Projects you have done.
This might be 6-10 months project with about $500/month or more depending on how many hours you put..
But first I will test selected bidder and give them little verilog code/small project to work on to test you knowledge. So please bid only for test project you will be working on. For whole project, I might create new contract. Test project/code I give you will include testing you skills on verilog, system verilog and more...If you are know verification, you have big advantage...
I think test I take will not take more than 10 hours to an expert...You will be given 3-4 weeks to complete you test..just have to spend 2-3 hours a week..I will also see your time arrangement and how you approach deadline and all stuff....As this test will take 10 hours and I might ask 3-4 of you to take it, I dont be paying that much for test..bidding should be between $50-$100..
Once I see responses and your test projects, I will choose one of you and you will be paid around $500 a month for working hardly 30 hours per month..
9 freelancers are bidding on average $144 for this job
I have a good working experience in Verification using system verilog, Comprehensive knowledge of the methodologies for implementing System Verilog Assertions to measure Functional Coverage and protocol checker.