I'm working on a small project which implements a simple (slow) serial CPU bus in a FPGA.
The CPU bus is 2 bits wide and uses a transition based protocol.
The code is written in VHDL and functional but the system contains bugs.
You will review my code, consult me how to improve it and try to find bugs.
The code base is only a few hundred lines and is simple in nature. The bug(s) can be in the code but also in my physical setup.
Communication will go through a chat application such as MSN, Google Talk, IRC (I'm open to alternatives).
My timezone is GMT+2.
I expect you to have a good knowledge of VHDL, Experience with Altera FPGA and the Quartus II development environment, basic to good knowledge of digital electronics.
A bonus upon succesful completion of the project is discussable.
Expected time needed is a few hours. An hourly fee can be agreed on.
12 freelancers are bidding on average €177 for this job
Hello, I have more than 3 years experience in VHDL and FPGA design. If you are interested you can send me Private Message to discuss about detailed price, time and everything. best regards Zoran
i have work experience of 7 yrs in VHDL programming on Altera Quartus II and Xilinx ISE....You can count on me for this work will not have any regrets..looking forward to hear from u