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VHDL tasks

I have some simple VHDL tasks. My deadline is tomorrow.

1. Suggest a structural and behavioral description of a bidirectional cyclic shift register.

2. Suggest a structural and behavioral description of a bidirectional arithmetic shift register. Use parallel generation operators and configuration options.

3. Create a subroutine that performs the conversion between the integer and bit_vector types. Create an object and an architectural body to check this feature.

4. Create a package that declares one constant and one function, and its body. Save the package and its body in some library. Demonstrate the use of the library and use context statement operators to use the content of the package without a prefix.

5. Consider the following code:

library ieee; use [login to view URL];

package config is

type type1 is record

f1 : std_logic_vector(31 downto 0); f2 : std_logic_vector(3 downto 0);

end record;

type type2 is record

f1 : std_logic_vector(31 downto 0); f2 : std_logic_vector(3 downto 0);

end record;

end config;

library ieee; use [login to view URL]; use [login to view URL];

entity Swap_1 is

port (Data1 : type1; Data2 : type2; sel : STD_LOGIC;

Data1Swap : out type1; Data2Swap : out type2); end Swap_1;

architecture Behave of Swap_1 is begin

Swap: process (Data1, Data2, sel) begin case sel is

when '0' => Data1Swap <= Data1; Data2Swap <= Data2;

when others => Data1Swap <= Data2; Data2Swap <= Data1;

end case; end process Swap; end Behave;

Compile this code. What is the problem? Suggest a fix. Now write a testbench and test your code. Have you considered all possibilities?

6. Fix the bugs and simulate the following model:

entity UpDownCount_Bad is

port( clock, reset, up: STD_LOGIC;

D: STD_LOGIC_VECTOR (7 to 0)); end UpDownCount_Bad;

architecture Behave of UpDownCount_Bad is begin process (clock, reset, up);

begin

if (reset = '0') then D <= '0000000'; elseif (rising_edge(clock)) then if (up = 1) D <= D+1;

else D <= D-1;

end if;

end if;

end process;

end Behave;

7. Create a function and procedure on the following declaration and check their work:

function Is_X_Zero (signal X : in BIT) return BIT; procedure Is_A_Eq_B (signal A, B : BIT; signal Y : out BIT);

27. Please create and check the architecture of the multiplier bodies according to the upcoming description of the object

entity Mult8 is

port ( A, B : STD_LOGIC_VECTOR(3 downto 0); Start, CLK, Reset : in STD_LOGIC;

Result : out STD_LOGIC_VECTOR(7 downto 0);

Done : out BIT);

end;

Skills: Electrical Engineering, Engineering, Verilog / VHDL

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About the Employer:
( 0 reviews ) Kyiv, Ukraine

Project ID: #19446192

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ahmedmohamed85

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inspiredwhiz

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kptechlead

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Saneru92

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