VHDL Verification Engineer -- 2

Closed Posted 3 months ago Paid on delivery

Campera Electronic Systems is planning to introduce a Verification methodology in the company verification flow for VHDL designs.

Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.

Engineering Electronics Verilog / VHDL Electrical Engineering FPGA

Project ID: #36673609

About the project

7 proposals Remote project Active 2 mos ago

7 freelancers are bidding on average €30/hour for this job


Hi there,I'm biddin on your project "VHDL Verification Engineer -- 2"Verilog / VHDL, FPGA, Engineering, Electrical Engineering and Electronics Campera Electronic Systems is planning to introduce a Verification methodol More

€46 EUR / hour
(41 Reviews)

Hi there

€27 EUR / hour
(4 Reviews)

Dear Andrea C. We went through your project description and it seems like our team is a great fit for this job. We are an expert team which have many years of experience on Engineering, Electronics, Verilog / VHDL, E More

€27 EUR / hour
(1 Review)

I am excited to submit my proposal for the job opening at Campera Electronic Systems, where you are seeking a professional with experience in implementing verification methodologies for VHDL designs. Having extensive k More

€23 EUR / hour
(0 Reviews)

I am a student from Indian Institute of Technology (IIT) Jodhpur with Computer Science and Engineering branch. I have been interested in Digital Electronics and have also completed a course in it with A grade. I would More

€20 EUR / hour
(0 Reviews)