VHDL Verification Engineer -- 2
€18-36 EUR / hour
Campera Electronic Systems is planning to introduce a Verification methodology in the company verification flow for VHDL designs.
Previous experience on one of the "standard" VHDL verification methodologies (UVVM, OSVVM) or framework (Vunit) is requied.
Project ID: #36673609
About the project
7 freelancers are bidding on average €30/hour for this job
Hi there,I'm biddin on your project "VHDL Verification Engineer -- 2"Verilog / VHDL, FPGA, Engineering, Electrical Engineering and Electronics Campera Electronic Systems is planning to introduce a Verification methodol More
Dear Andrea C. We went through your project description and it seems like our team is a great fit for this job. We are an expert team which have many years of experience on Engineering, Electronics, Verilog / VHDL, E More
I am excited to submit my proposal for the job opening at Campera Electronic Systems, where you are seeking a professional with experience in implementing verification methodologies for VHDL designs. Having extensive k More
I am a student from Indian Institute of Technology (IIT) Jodhpur with Computer Science and Engineering branch. I have been interested in Digital Electronics and have also completed a course in it with A grade. I would More
