this project is Profiling a Pipelined RV32I Implementation. needs to do some change to [login to view URL] and [login to view URL] and acchive the best effort pipeline implementation on [login to view URL] and make sure total Clock Cycles from the execute stage is less than 70,000. It should achieve the highest possible wall-clock speed, taking the clock speed into account. It will be evaluated using a vanilla rv32i implementation, without the Mul instruction. and a report addressing the questions listed in the file attached.