Completed

Pipelining a RISC-V processor

this project is Profiling a Pipelined RV32I Implementation. needs to do some change to [login to view URL] and [login to view URL] and acchive the best effort pipeline implementation on [login to view URL] and make sure total Clock Cycles from the execute stage is less than 70,000. It should achieve the highest possible wall-clock speed, taking the clock speed into account. It will be evaluated using a vanilla rv32i implementation, without the Mul instruction. and a report addressing the questions listed in the file attached.

Skills: Software Architecture

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About the Employer:
( 0 reviews ) Irvine, United States

Project ID: #29478906

Awarded to:

GrintaLab

I'm computer engineer and lecturer with more than 15 years of expertise. I'm professional with Computer architecture , designing the datapath with pipleining for AVR , MIPS , and RISC -V. I'm also professional with bl More

$140 USD in 4 days
(1 Review)
2.3