codes are in pdf.
compile it and correct the errors.
it has to work at XILINX 10.1
just create an errorless project.
all codes are ready in pdf.
WORKING SIMULATION IS ENOUGH.
CORRECT ERRORS, maybe there is no error but i can not run simulation.
10 freelancers are bidding on average $49 for this job
i have a very good exp in VHDL and VERILOG. i am also a ceritified by Indian institute of VLSI Design and training, Bangalore. i will complete this project in a week.