Given the Open Cores from the open cores project I want a simple module that is able to do the following on a Xilinx ZedBoard:
1. Given 256 bit BITKEY, scramble the input with a hard coded IDKEY in the FPGA and provide a AESKEY
2. The same response needs to be piped to an AES256 module from OPEN CORES in order to encrypt/decrypt a stream of data
1. 256 BITKEY
2. selector BIT for encrypt decrypt (the output needs an XOR for decrypt)
3. stream of data as 256 bit 'chunks'. The architecture here should be trivial to support a driver easily.
1. 256 AESKEY
2. stream of encrypted/decrypted data as 256 'chunks'
This should be the bulk of the work; There needs to be diagrams and specifications for reproduction on another ZedBoard. This should include:
1. Layout of blocks
2. FPGA registers used and how the driver should interact with them
3. Maximum bandwidth achieved
4. Tests that were executed to prove design and plots of the execution of these tests. A test suite should be present for both encryption and decryption with different IDKEY.