assigment VHDL -- 2

1. Implement 2-bus processor with a hardwired control unit: The processor has the following characteristics. • Instructions: Add, Or, Sub, Ori, Xor, Ld, St, La, Br, Brnz, Stop, Shl. • Data bus is 32 bits. • Address bus is 16 bits. • 24 general purpose registers. • Shift instruction should be executed within one clock cycle.