9-bit CPU: Register file, ALU, and fetch unit
$30-250 USD
Paid on delivery
In this lab assignment, you will design the top level, register file, control decoder, ALU
(arithmetic logic unit), data memory, muxes (signal routing switches), lookup tables, and fetch
unit (program counter plus instruction ROM) for your CPU. For this and future designs, we want
the highest level of your design to be a schematic and [System]Verilog code...
if you are intersted in let me know . There is instruction that I will shrae with you.
Project ID: #21938846
About the project
8 freelancers are bidding on average $150 for this job
Dear sir I have more than 10 years experience in digital design using verilog and system verilog please check my profile also please message me so that we can discuss
Hi, i am electrical engineer, i can design the ALU using verilog HDL,....................................
Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG and about 200 JOB completed. I am really suitable for job d More
I have well experienced in doing such kind of jobs.......................................................................................................
Hi I have been working on verilog-vhdl and xilinx and altera(intel) FPGAs by more than 6 year. lets discuss the requirements, the price mentioned is negotiable according to your exact requirements. Thanks
I have 10 years of experience in design and verification using Verilog. Please message me. Best regards.
Hello, I am interested in your IDEA, Can we share with our idea each other? I think you have some mistakes now, thank you!!!