9-bit CPU: Register file, ALU, and fetch unit

Completed Posted 4 years ago Paid on delivery
Completed Paid on delivery

In this lab assignment, you will design the top level, register file, control decoder, ALU

(arithmetic logic unit), data memory, muxes (signal routing switches), lookup tables, and fetch

unit (program counter plus instruction ROM) for your CPU. For this and future designs, we want

the highest level of your design to be a schematic and [System]Verilog code...

if you are intersted in let me know . There is instruction that I will shrae with you.

Verilog / VHDL Microcontroller Electronics Electrical Engineering FPGA

Project ID: #21938846

About the project

8 proposals Remote project Active 4 years ago

Awarded to:

raulbehl

Hello! Please check my reviews and profile to know more about me and my work. I’ve helped many students in completing there computer architecture courses and should be able to help you out as well. Please do contact to More

$100 USD in 7 days
(82 Reviews)
6.2

8 freelancers are bidding on average $150 for this job

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using verilog and system verilog please check my profile also please message me so that we can discuss

$111 USD in 1 day
(448 Reviews)
7.9
uetian09ee506

Hi, i am electrical engineer, i can design the ALU using verilog HDL,....................................

$150 USD in 3 days
(270 Reviews)
7.2
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG and about 200 JOB completed. I am really suitable for job d More

$200 USD in 3 days
(89 Reviews)
6.4
thasleemkamila

I have well experienced in doing such kind of jobs.......................................................................................................

$50 USD in 3 days
(47 Reviews)
5.7
Fpgageek

Hi I have been working on verilog-vhdl and xilinx and altera(intel) FPGAs by more than 6 year. lets discuss the requirements, the price mentioned is negotiable according to your exact requirements. Thanks

$250 USD in 7 days
(30 Reviews)
5.5
hungfreelancer

I have 10 years of experience in design and verification using Verilog. Please message me. Best regards.

$88 USD in 3 days
(8 Reviews)
4.2
Muratzz

Hello, I am interested in your IDEA, Can we share with our idea each other? I think you have some mistakes now, thank you!!!

$250 USD in 3 days
(4 Reviews)
3.0