Completed

DDR3 controller for / series FPGA

We want a DDR3 controller for a 7 series FPGA with the following specification:

- DDR3 Speed: 533MHz (DDR3-1066)

- DDR3 component: MT41K1G8SN-125:A

- FPGA: XC7K160T-2FFG676I

The controller shall have the following interfaces to the top level:

- AXI slave for incoming write data - 32bits width

- AXI master for outgoing read data - 32bits width

- write enable signal which enables the AXI slave interface

- read enable signal which enables the AXI master interface

- if both interfaces are enabled at the same time, the write interface has priority

- both AXI interfaces shall have internal clock independent FIFOs

- read clock and write clock on the top level interface must be completely independent

- a global, synchronous reset (synchronous to MIG ui_clk)

Functional description:

Write:

When the user initiates a write command, the controller must be able to receive data with a maximum speed of 200MHz continuously, until DDR3 memory is full. The user may stop the transfer at any point. The controller must be able to handle data counts from 1 sample (32bits) up to the maximum DDR3 memory size.

The write interface must be axi-stream compliant.

Read:

When the user initiates a read operation, the controller must be able to send data with a maximum speed of 200MHz continuously, until DDR3 memory is empty. The user may stop the transfer at any point. The controller must be able to handle data counts from 1 sample (32bits) up to the maximum DDR3 memory size.

The read interface must be axi-stream compliant.

General:

The controller must record the number of samples written thru the write FIFO.

If the user wants to read more samples thru the read FIFO than samples are available in the DDR3 memory, then the "tvalid" of the AXI read interface shall remain low.

Important: The entire source code must be done in Verilog.

The clocks required by the design will be provided from the top level. No additional MMCMs or PLLs shall be used inside the controller.

Please only apply for this project if you have experience with 7 series FPGAs and DDR3 in combination as well as the native interface for the Xilinx MIG.

Skills: Electronic Design, FPGA, Verilog / VHDL

See more: fpga memory interface, xilinx memory interface generator tutorial, xilinx sram controller, xilinx mig user guide 2017, xilinx mig ecc, xilinx mig user guide 2018, mig 7 series example design, xilinx ddr3 controller

About the Employer:
( 0 reviews ) Graz, Austria

Project ID: #19072208

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ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a More

€250 EUR in 10 days
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6 freelancers are bidding on average €722 for this job

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using FPGA also I have done many projects using MIG interface, please message me so that we can discuss more details Best regards

€833 EUR in 3 days
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teamfpga

I am Electrical Engineer and have an expertise on the Verilog/VHDL. I am working on these languages since six years I have a professional team of Electrical Engineers with me. We have sound hands on program More

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ayesha0124

Hi there, I have checked the details. I have rich experience with Electronic Design, FPGA, Verilog / VHDL. Please initiate the chat so we can discuss this job in detail.

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Ivan927

Hello! I am very interested in your post project. i am really looking for this kind of project for a long time in freelancer since i have rich experience on it. I think this project is very suitable for me and i am More

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thoapham177

Hi Sir, I have two projects working on DDR interface. And have some module code fot DDR interface now. You can contact me to get this code immediately. Thanks, Vu

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