Dear sir,
I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and others.
I have done master project on RISC-V. We run many algorithms on it and report the power on vivado. I can do your project, it is kind of similar.
Please contact me to discuss more about this project.
Kindest regards.