Budget $10-15 USD
Design a block diagram for a smart watch using vivado.
Skills: Verilog / VHDL, Electronics, Circuit Design, FPGA, C Programming
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Project ID: #30916071
I have experience in VLSI RTL design and verification ,i am sure i will help in your project, i have worked on xilinx, vivado, questasim ect.
for more details you can freely contact to me.
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