Completed

Development activity on Xilinx Spartan

1. Configure 4 UARTs (Rx Only).

2. Configure 2 SPI Slaves.

3. Data coming on UARTs are split into two groups.

a. 2 UARTs first SPI slave and another 2 UART data Second SPI slave.

4. Data pattern on UART will be "Magicnumber(4 bytes), Length (4 bytes), Payload".

UART , SPI slave and required FIFO modules need to be developed in VHDL / verilog.

Skills: FPGA, Verilog / VHDL

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