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flaoting point adder in fpga help

ok before we had a paper to review about floating point adder in fpga i already did but there is the furue work of that paper talking about specific topic for improvment if u could help me with it (far and close path algorithms).

Skills: Verilog / VHDL, Electrical Engineering, Electronics, FPGA, Engineering

About the Client:
( 1 review ) Al Wajh, Saudi Arabia

Project ID: #33741812

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faizanmaqbool695

Hi,Hope you are doing well! I have checked your requirement, yes I can do it, because I already work on similar requirement in past. If you have interested in my proposal, please contact me. I will do my best in order More

$70 USD in 2 days
(45 Reviews)
6.0

10 freelancers are bidding on average $145 for this job

Lightcanon

Hello. I am Digital design engineer with +6 years of experience in Verilog/VHDL RTL coding. I have worked on multiple floating/fixed point operations in Verilog, like Addition/Subtraction, Division and inverse square r More

$250 USD in 7 days
(99 Reviews)
6.8
(40 Reviews)
5.8
azraazeen9

Hello, i am ready exited to work you as i read your job description flaoting point adder in fpga help Hope for your very soon reply. Thank you

$258 USD in 3 days
(6 Reviews)
4.4
senthilps3

Hi I am a researcher and circuit designer. I have completed phd floating point arithmetic in fpga implementation. You can check my profile for my projects and research. I can sure to complete your projects in floating More

$140 USD in 7 days
(16 Reviews)
3.7
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3.3
VirtualBrainInc

Hello, I have briefly read the description on; Engineering Electronics Verilog / VHDL Electrical Engineering FPGA project, and I can deliver as per the requirements however I need us to discuss for more clarity on the More

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ProfessorxCorp

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0.0
kausthubha21

I am a FPGA Engineer by Profession with good experience. I have worked on many projects till date and I hope I can complete your requirement. Please let me know if you have any further queries.

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transformyou03

Present I have been working on 5G Transmitter designing in RTL verilog [login to view URL] that I designed this floating point [login to view URL] I can defintely assure regarding [login to view URL] is why I am doing it at low cost because this i More

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0.0