I need a VHDL/Verilog designer -- 3

I will be implementing this on vivado 2019, with using the zynq xc7z020-1clg400c chip

Stopwatch with Start, Stop, Increment, and Clear Functionality

Create a four-digit stopwatch on your Blackboard, using the seven-segment display as an output device. The stopwatch should count from 0.000 to 9.999 seconds and then roll over, with the count value updating exactly once per millisecond.

The stopwatch uses three pushbutton inputs: start, stop, increment, and clear (reset). The start input causes the stopwatch to begin incrementing at a 1KHz clock rate (i.e., one count per millisecond); the stop input stops the counter from incrementing but leaves the display showing the current counter value; the increment input causes the displayed value to increment once each time the button is pressed regardless of how long the increment button is held down; and the reset/clear input forces the counter value to zero.

Hint #1 - System block Diagram

Hint #2 - Decimal Counter

Hint #3 - Seven Segment Display Controller

these hints will be given if the job is accepted. (just diagrams and internal schematic of each device show in the pictures). Full details given if job accepted.

Skills: Verilog / VHDL, Electronics, Microcontroller, Electrical Engineering, FPGA Coding

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Hi I am an Electrical Engineering. I have comprehensive knowledge in VHDL and verilog. I have done many projects of FPGA. Let me know what exactly do you want. Fell free to contact

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Hello, I am a digital design engineer and VHDL/Verilog expert with +5 years of experience. I can help you easily in this project. Contact me to discuss more.

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I need a VHDL/Verilog designer -- 3 I am a professional Ph.D. writer and holds an MBA degree. I will provide exceptional work with 100% perfection and Turnitin report as well. I deem fit to deliver it as expected. I ca More

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