Completed

Verification of MESI protocol using System Verilog and UVM

Awarded to:

kundanvaghela

i have 2.5+ year experience in design and verification, i have done 4 bigger projects in SV/UVM, AXI , AHB , RISC V etc. i have done 30+ project in verilog/VHDL, i will done your project perfectly and on time, i w More

₹2000 INR in 3 days
(11 Reviews)
3.7