Closed

VHDl Based design

ADS7038

Xilinx Virtex

DAC7750

If 1Vpp is given to ADS7038 it should convert that input into digital signal and store it into the memory of Xilinx Virtex FPGA and DAC7750 should convert the digital stored data into analog 1Vpp.

Write VHDL code for communication with ADS7038 and DAC7750 where FPGA Virtex is the master controller. Write the code on Xilinx Vivado and send simulation pictures.

The code must be synthesisable.

Also include a short description of how the communication works with these devices.

Skills: Verilog / VHDL, FPGA, Electronics, Electrical Engineering, Microcontroller

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Project ID: #31031406

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Gerrard97

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Valuesolutions

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hivongmoi1234

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cmsivolella

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