Closed

VLSI design and testability using SPICE/ Verilog/VHDL

10 freelancers are bidding on average $486 for this job

ahmedmohamed85

A proposal has not yet been provided

$444 USD in 3 days
(287 Reviews)
7.5
loi09dt1

A proposal has not yet been provided

$750 USD in 15 days
(89 Reviews)
6.3
mze5583fac62088c

Hi Muhammad, my name is Zeeshan. Please share more details of your project. Relevant Skills and Experience I am MS Electrical Engineer and have extensive experience with Spice and verilog. Proposed Milestones $333 US More

$333 USD in 10 days
(0 Reviews)
0.0
rubelsarkar161

Hi, I do work as a IC Layout and system design engineer in Bangladesh. Hope I can help you Or, if you need any help regarding IC layout mask design you can contact

$555 USD in 4 days
(0 Reviews)
0.0
faaan37

Hi I would love to do your task. If you hire me, i won't let you down. I can provide you all these things with unlimited revisions till the satisfactorily completion of [url removed, login to view] for your message .Thank you

$444 USD in 15 days
(0 Reviews)
0.0
ganewatthe

I need more information on the project task. Relevant Skills and Experience I'm familiar with verilog/verilog-a/verilog-ams and spice. Stay tuned, I'm still working on this proposal.

$333 USD in 10 days
(0 Reviews)
0.0
iffi37

Hello I would love to do your task. If you hire me, i won't let you down. I can provide you all these things with unlimited revisions till the satisfactorily completion of [url removed, login to view] for your message .Thank you

$444 USD in 12 days
(0 Reviews)
0.0
elkhamlichi6m

hi sir you can hire me

$333 USD in 2 days
(0 Reviews)
0.0
hytr21

I try my best if you give a chance ☺

$666 USD in 5 days
(0 Reviews)
0.0
ChewGekKhim

I am a developer with sufficient experience in VHDL programming A few days ago I used Cyclone 4 to measure the location of the source of ultrasound using ultrasound sensors and signal processing. In addition,I had fi More

$555 USD in 10 days
(0 Reviews)
0.0