should develop SPI single master-single slave verification IP using UVM and verify different test scenarios.
should mimic the BFM design in driver without using DUT and verify all the modes of SPI and some error conditions and create coverage statistics for the verified module.
Skills: Very-large-scale integration (VLSI), Front-end Design, Simulation, Verilog / VHDL
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Hyderabad, India
Project ID: #29431468
