SOC Static Time Analysis engineer (India)

Job Description:

Tasks to be executed:

Lead the team for SOC Static Timing Analysis STA and for the Power checks preliminary to SOC Netlis Sign Off.

Setting Up the STA environment for the Full Soc, including Constraints.

Leading the STA activities for the timing verification at top level.

Leading the SoC Netlist Synthesis at top level,

Leading the SoC top level Clock networking , including mixing, cross domain checks.

Chip level STA environment setup , STA constraints and.,

STA Synthesis runs

STA Lead : Lead SoC top timing lead, taking care of flat/hier synthesis runs for subsystem and SoC Top

entire SoC top clocking network and muxing concepts, debugging/analysis issues related to this clock network, Cross domain clocking checks and constraints validation,

STA flow support/automation

Functional/timing ecos debug/anslysis, ,

Good knowledge on synthesis (hands-on is preferable)

Optional : Good to have PTPX (power analysis) working experience as well

I

Skills: Wireless, Electrical Engineering, Network Administration, Telecommunications Engineering, Electronics

Project ID: #35709792