SystemVerilog solver and editor

by MoemenAhmed1
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This is a parser to SystemVerilog syntax, it's intended to parse data declarations and constraints, then convert them to a specific format that is suitable for our solver tool. A GUI-based parser and solver The parsing process starts from a modified subset of regular expressions and grammar rules that describe SystemVerilog syntax, then I use PyPEG (a parse tree generator) to generate the parse tree of the input SystemVerilog syntax. I use a modified subset of SystemVerilog grammar rules as I'm interested only in the data declaration and constraints parts in SystemVerilog. For more details, please see the following link: https://github.com/bit-zone/SystemVerilog-Specific-Parser

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About Me

I'm a software engineer with a Bachelor's degree in Computer Engineering. Skilled in Machine Learning, Data Analytics, Python, C, C++, Desktop Applications, Embedded Systems, and Hardware Digital Design.

$3 USD/hr

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