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India (10:20 AM)
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Joined on March 16, 2007
Graduate in VLSI, and having cutting edge exposure from minarc, ISEP, Paris in microelectronics. I am here to broaden the horizon of the challenges. I have published a paper in IEEE-TED.
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Experience
Contract engineer
Oct, 2007 - Jun, 2008
•
8 months
DRDO
Oct, 2007 - Jun, 2008
•
8 months
I was involved and evolved in developing in web pages and developing the online web pages for the company.
Oct, 2007 - Jun, 2008
•
8 months
Education
Vellore Institute of Technology
2008 - 2010
•
2 years
M.Tech
India
2008 - 2010
•
2 years
Visvesvaraya Technological University
2002 - 2006
•
4 years
B.E.
India
2002 - 2006
•
4 years
Qualifications
Designing
2010
Paper publishes in designing in IEEE-TED
2010
Publications
30nm Tunnel FET with Improved Performances and Reduced Ambipolar Current, published in IEEE-TED (Transaction on Electron Device), TRANSACTIONS ON ELECTRON DEVICES
Anju Gupta
To boost the on current with the source edges.
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