I have started my PhD studies in microelectronic design at LSI-DIE@ETSIT-UPM. For the time being, I am evaluating aging effects on CMOS due to PVTs. Looking forward smart new designs to overcome the parasitics appearing in sub-40nm technologies. Collaborating as instrumentation engineer (PCB design and layout, RTL coding) in rad-hard experiments.

Fellow@CERN in BE-CO-HT. Worked as an Electronics Engineer in Mixed-Digital Design. I was in charge of boards bring-up for the renewal of synchronization legacy systems, currently running all along CERN facilities. The tasks include: - IP core design, verification and testing. Integration with other modules (such as MGT lines) and interfacing with third-party devices. Working on Xilinx Spartan6. - PCB design, layout revision and board testing. Manufacturing Test Suite for detecting assembly failures and increase reliability of the whole product. - Provide documentation for both legacy devices and new designs. - Contributor to Open Hardware Repository: http://www.ohwr.org