harshithcs

> RTL design engineer with 5+ years of industry experience.. > Experience in digital design using Verilog/VHDL hardware description language. > Experience in micro-architecture/logic design of complex blocks and subsystems > Experience on high speed and low power RTL designs,STA > Expertise in FPGA design flows > Experience in Verification using system verilog. > Experience in working on FPGA boards(Xilinx) > Experience on Xilinx Tools - ISE 14.7, Vivado 2014.4 > Mentor graphics simulation Tools - Modelsim, Questasim > Good Knowledge on H.264 video compression > Experience on transport protocols - Uncompressed Video transport over SDI (SD/HD/3G-SDI), Ethernet(RFC4175) - Compressed Video transport ASI/TS, Ethernet(RFC6184) - PCM, Dolby, Dolby digital audio over Ethernet as per RFC standard > Forward error correction(FEC) and jitter handling(SMPTE 2022-5)