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ASIC
Digital Design
Digital Electronics
FPGA
Verilog / VHDL
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$10 USD / hour
Flag of INFlag of IN
junagadh,
india
$10 USD / hour
It's currently 9:22 AM here
Joined January 10, 2020
1 Recommendation

Kundan V.

@kundanvaghela

4.9 (12 reviews)
4.9 (12 reviews)
3.8
3.8
$10 USD / hour
Flag of INFlag of IN
junagadh,
india
$10 USD / hour
100%
Jobs Completed
71%
On Budget
71%
On Time
18%
Repeat Hire Rate

ASIC/FPGA/SoC design and verificaion engineer

71% FOR ON TIME AND ON BUDGET IS NOT RIGHT..... hi i have done more than 20 projects on UVM,systemverilog and verilog , VHDL you can see some big projects below, 1s FUNCTIONAL VERIFICATION OF UNIVERSAL MEMORY CONTROLLER:- Description: Universal memory controller supports a variety of memory devices, 8 Chip selects, each uniquely programmable. SDRAM,SSRAM, FLASH, ROM and many other devices supported. It has feature like Burst transfers and burst termination Industry standard WISHBONE SoC host interface Responsibilities: Analysis of the specification document. Listing down feature. Developing test plan. Template environment coding of test-bench architecture. Coding test-bench component and integration of them. Connect different types of memory like SRAM.SDRAM, and FLASH to DUT. Developing sanity test cases and functional test cases. Functional and code coverage Setting up regression and verification closure HVL:- System Verilog Tool:- Questa sim 10.4e 2nd AHB Interconnect Functional Verification using UVM & System Verilog Test plan development Developing test bench architecture Verification closure using Functional coverage & code coverage as closing criteria. Methodology: UVM 3rd Development of AXI 3.0 VIP and validation using AXI slave VIP Description: AXI interconnect is configurable design for connecting multiple masters to multiple slaves. Design also has a configuration interface for configuring slave address ranges. As part of design verification we verified interconnect for different number of masters, slaves and slave address range configurations. Responsibilities: Test plan development TECHNICAL SKILL Developing test bench architecture coding Verification closure using Functional coverage and Code coverage as closing criteria HVL:- System Verilog Tool:- Questa sim 10.4e skills; Digital design UVM SystemC System Verilog Verilog VHDL UNIX scripting PERL
Freelancer
Verilog / VHDL Designers
India

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Reviews

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Showing 1 - 5 out of 12 reviews
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5.0
₹400.00 INR
Good work. i would like to hire him in future projects
Verilog / VHDL
Digital Design
FPGA
Digital Electronics
ASIC
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Flag of IN Asiammal M. @reyasparveen
8 months ago
5.0
€120.00 EUR
perfect!!!!!!!!!!!!!
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Flag of ES Alberto A. @aalbe77
1 year ago
5.0
$30.00 USD
He did really good work with sufficient time it will be not the last time to work with him
PLC & SCADA
Digital Design
FPGA
Digital Electronics
ASIC
M
Flag of AE Salman M. @MariamAlshamsi
1 year ago
5.0
€25.00 EUR
he is really good at timing, it was really nice to work with him
Verilog / VHDL
Digital Design
FPGA
Digital Electronics
ASIC
P
Flag of LT Mustafa Y. @Piolin06
1 year ago
5.0
€20.00 EUR
Good job!!!!!!!!!!!!!!!!
Verilog / VHDL
Digital Design
FPGA
Digital Electronics
ASIC
User Avatar
Flag of ES Alberto A. @aalbe77
1 year ago

Education

B.E(EC)

Gujarat Technological University (GTU), India 2014 - 2018
(4 years)

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Verilog / VHDL
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Digital Design
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Digital Electronics
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