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- 100%Jobs Completed
- 71%On Budget
- 74%On Time
- 16%Repeat Hire Rate
Project for Rajagopal S. -- 2
“great work He is very friendly and always available.”Ramazan K. 5 months ago
“great to work with...”Rania E. 5 months ago
Help on a simple Altera FPGA test case
“Excellent freelancer, he knows very well his job and is a true professional. Highly recommended.”Christos N. 5 months ago
Tic Tac Toe Game
“work on time and high quality”Token K. 6 months ago
Project for Rajagopal S. -- 3
“Great Work”Fahad R. 6 months ago
Project for Rajagopal S.
“So far, so good.”Joao A. 7 months ago
Senior verification engineerJul 2016 - Nov 2017 (1 year)
Block level verification of ethernet switches.
Verification engineerJul 2013 - Jun 2016 (2 years)
Verification of ethernet switch(both custumer end switch, ISP switch) ,Central memory management controller using Systemverilog,UVM.
Asic Design/verification engineerJun 2011 - Jun 2013 (2 years)
Verification of ethernet switch ,scheduler,Txole, DMA (AXI) using System verilog UVM.
BE2007 - 2011 (4 years)
Diploma in ASIC (2011)RV -VLSI design centre
Whole flow of ASIC with hands on project(Design,DV,STA,PD,Layout).
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