In this lab assignment, you will design the top level, register file, ...tables, and fetch unit (program counter plus instruction ROM) for your CPU. For this and future designs, we want the highest level of your design to be a schematic and [System]Verilog code... if you are intersted in let me know . There is instruction that I will shrae with you.
I need a small CPU project prepared, to teach and demonstrate CPU construction. It sh...and code in my own block, and assuming all is good, will result in no change of system. And of course, machine language codes. This will be used to teach an AP class. System Verilog. [login to view URL] is a great example of what I am looking to teach with an FPGA
SITUATION: I have a VHDL design for a custom processor + peripherals that needs to go into an FPGA. It passes functional simulation that uses VHDL testbenches. I am in the process of adding VHDL checkers. This design needs to pass timing simulation with a (soft) target frequency of 50 MHz, be programmed into an FPGA, and be verified using an off-the-shelf