1. Can You make your own version of hardware decoder based on the decoding algorithm. t...should be remain the same is 64×64,(the decoding methods SISO decoding and Chase Pandiah, type 2 Chase algorithm) and after simulate the decoder on Xilinx ISE and coding in VHDL. 2. and write a brief report explanation how is the hardware structure work and etc.
BId only if u can do only the second...dropping it and seeing it through a stereoscope lensIn perspective projection and the use of two center projection (off-axis projection) 2,Implement hardware system using vhdl language and xilinx 9.2i software And executed on spartan -3e linen The graphic is displayed on an external screen only the second Part
in this project i need just read a analog signal on altera cyclone 5 board and also to realize pt1 element with simple response a(t)=(1-e^-t/T)....it's a simple project and i can explain you in more detail ....so i just want this to signal at the out i.e on gpio pins
working with a grideye infrared sensor and looking to send the data through a wifi Cypress connection. We have some experience with this already but i am looking ...this so that we can work back and forth to get this up and running. I would like to send the data to a be read out with a Visual C sharp interface. Experience with FPGA and VHDL is a bonus
I require source code for the design and simulation verification of a calculator (Not + - / * operations) with slightly more experienced VHDL'ers can be selected for th...require source code for the design and simulation verification of a calculator (Not + - / * operations) with slightly more experienced VHDL'ers can be selected for this quick project
Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No othe...
Hi, This project is for a team of VHDL expert and Java expert. I have a dev. FPGA board embedded the chip AD9764. This is the DAC. It embeds the chip ADS5522 too. This is the ADC. I already have a not-completed project written in vhdl including modules parts of this project. I need you to simulate and fix the data transmission part between the client
Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow)...implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.
I want to do a VHDL project on ModelSim, all what you need will be in the attached document, i will need a report for the whole project ( explaining every file in the project and what it does ). I want phase 1 ( Design ) ASAP and the rest of the project within a week ( Maximum 10 days ). Please read the document carefully and if you have any questions
I am currently working on peak detector using VHDL entry (Modelsim and Xilinx), to design logic design in FPGAs to fulfill my free time. There are two parts, which are command processor and data processor. However, I have completed the data processor part, so only command processor left and I have no idea how to complete it. I plan to accomplish this
I need to create and minimize 2 small VHDL entities and their corresponding architectures. Can anyone help? I will provide with some files that are the basics to this, but still need to create 2 more. You need to be expert in VHDL language and have knowledge of computer architecture.
A code that will read data from RFID tag 1 using a RC522 Rfid reader and verify that to a stored value. Upon successful authentication, it will read data from RFID Tag 2. Then the program will generate a random number and store it in RFID tag 1 and also update the previous system stored value of tag 1.