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ahmedabad, india
It's currently 1:15 PM here
Joined December 2, 2012
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Nishant S.
@saksenanishant
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ahmedabad, india
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ASIC DESIGN and VERIFICATION ENGINEER
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Portfolio
Portfolio
Internship Certificate
Experience of tools
Internship Certificate
Experience of tools
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Experience
ASIC DESIGN ENGINEER
Mar 2012 - Present
Technical Experience : ASIC Design Cycle, RTL level Functional Verification.
OVM verification methodology, Code Coverage, assertion
EDA Tools (VLSI) : Modelsim, Simvision, Quartus-II, Xilinx ISE 10.1,QuestaSIM
EDA Tools (Embedded) : Keil uvision 4,Mplab
Hardware Description Language : VHDL, Verilog, System Verilog
Programming Languages : C, C++, Embedded-C
Protocol Knowledge : PCI-Express 2.0, UART, I2C
ESDK : Virtex-4,Spartan-I
Education
Bachelors of Engineering
(4 years)
Qualifications
Internship completion certificate
Space Application Center, ISRO
2011
On successful completion of final semester B.E training at SAC-ISRO , I was given the certificate.
Development of Ground Checkout Unit (GCU) modules for testing Payload controller (8th semester).
o Organization: Space Application Centre (SAC-ISRO), Ahmadabad.
o Training as: Intern
o Topic: Development of GCU using MicroBlaze processor on SPARTAN FPGA 3E Kit.
o Description: Designed and developed MicroBlaze processor based standalone GCU, which can test payload controller as commanded by PC using UART.The design consists of Digital to Analog converter module, Data Capture module, Timing Signal Generator module.
o Processor: 32 -Bit Micro Blaze Processor.
o Languages used: Embedded C and VHDL.
o Tools used: Xilinx EDK 10.1, Xilinx ISE 1.5i software.
o Duration of project: 20/01/2011 to 29/04/2011
Publications
32-bit floating coprocessor verification
SAC
Software development in C for 8051 based On Board Controller (OBC) - ASIC in Kiel for
32 bit Floating point and 8 bit Integer implementation of Phase Computation for Beam Steering of Active Phase Array Radars.
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