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Memory Module for MIPS-32 Architecture using FPGA (Urgent)

I am looking for some one to make a memory that has a hold staus while memory is fetching memord ,the input pins are Adsress (32-Bits) ,Data (32-Bits) ,Read and write seprate (1 Bit each), abd for out put must have a hold output (1-Bit) which should be at logic high when memory is busy while reading.

Skills: Electrical Engineering, Electronics, Verilog / VHDL

See more: vhdl and verilog, one bits, bit bits, 1 bits, vhdl fpga, verilog vhdl, memory, memory c, fpga vhdl, fpga verilog/vhdl, read memory, verilog write, verilog vhdl fpga, fpga vhdl verilog, fetching data, output using, bits mips vhdl, mips verilog, bits logic, electronics module, mips fpga, vhdl bit mips, fpga read, pins, data architecture

About the Employer:
( 0 reviews ) Cardiff, United Kingdom

Project ID: #1131687

3 freelancers are bidding on average $333 for this job

usamacpp

Please check PMB

$500 USD in 5 days
(2 Reviews)
3.7
ritikap

I can give you the best result in the desired time.

$250 USD in 2 days
(0 Reviews)
0.0
abdkhan

i have already done that please pm me for further details

$250 USD in 0 days
(0 Reviews)
0.0