Memory Module for MIPS-32 Architecture using FPGA (Urgent)

I am looking for some one to make a memory that has a hold staus while memory is fetching memord ,the input pins are Adsress (32-Bits) ,Data (32-Bits) ,Read and write seprate (1 Bit each), abd for out put must have a hold output (1-Bit) which should be at logic high when memory is busy while reading.