Atlys xilinx jobs
We are searching for an embedded SW developer, with knowledge of ARM architectures, AMBA bus. SoC like Xilinx Zynq, FPGA+ARM, soft processor are required. C/C++ for embedded systems. The company is searching for long term collaboration
I am looking for an experienced Verilog or VHDL engineer to help me explain and design Number theoretic transform (NTT) which is the most efficient method for multiplying two polynomials of high degree with integer coefficients, using FPGA. The project has specific requirements and I will provide detailed specifications. The desired implementation platform is Xilinx FPGA using Vivado and the deadline for the project is 1-2 weeks. Ideal skills and experience for the job include Verilog or VHDL programming, FPGA design, and NTT knowledge.
The goal of this project is to design and implement an high speed communication interface on a Xilinx ZYNQ platform. Hardware is already available and will be accessible remotely.
I am looking for an experienced freelancer to work on an FPGA based project. The main goal of this project is performance optimization, and I am looking for someone with experience using the Xilinx platform, and coding in VHDL. I am looking for someone who can ensure that the project turns out as expected and meets all my requirements. Additionally, I would like the outcome of this project to have a positive impact on my organization's performance. The freelancer I choose must have in-depth and up-to-date knowledge of the FPGA architecture as well as memory control, interfaces, and system design. He/she should also possess excellent programming experience and be able to provide detailed reports and documentation in a timely manner. Moreover, I need assurance that this project...
I am looking for a freelancer who can design and implement an LMS adaptive filter in the structural level modeling using an FPGA. The ideal candidate should have experience with Xilinx FPGA devices and be able to work with high-frequency signals (>10kHz). The desired level of accuracy for the filter design is medium (±1% error). Specifically, the project requirements include: - Design and implementation of an LMS adaptive filter in the structural level modeling using an FPGA - Working with high-frequency signals (>10kHz) - Experience with Xilinx FPGA devices - Achieving medium accuracy for the filter design (±1% error) If you have the necessary skills and experience, please submit your proposal.
I am looking for an experienced freelancer to help me with a project where I need to transmit data from a Xilinx FPGA to a PC through UART. The data size that needs to be transferred is 1-10KB. It is critical that the selected freelancer has prior experience in this specific area. I'm looking forward to working with you!
I am looking for a freelancer who can help me speed up TFTP transfer in my Xilinx SP-605 FPGA board (Spartan 6). Currently, the transfer speed is about 1MB/s and I need it to be faster. Ideal skills and experience: - Experience with Xilinx SP-605 FPGA board (Spartan 6) - Experience with Xilinx Platform Studio, and Xilinx SDK (microblaze) - Strong understanding of TFTP transfer protocols - Knowledge of hardware constraints and optimization techniques - Experience with network interfaces and memory bandwidth Constraints: - Must consider hardware constraints - Must use Xilinx SP-605 FPGA board (Spartan 6) - Must consider software constraints - Use Xilinx Platform Studio (XPS) 14.1 - SDK - Microblaze I already have an existing XPS pro...
As part of a development project, I need help designing verilog code on Xilinx. I'm looking for experienced freelancers with the technical skills to properly implement the design. I need complete control when it comes to providing feedback and making sure the progress is on track. The right candidate should have a solid track record and demonstrate their expertise in the same field before applying to the job.
I'm looking to hire an experienced Xilinx FPGA programmer to help with a project. Located near Mumbai suburb. The ideal candidate should have extensive knowledge in FPGA programming and specifically working with Xilinx FPGAs. Please provide some proof of your skills and experience with coding for FPGAs. I look forward to hearing from you soon!
BCD multiplier development using Verilog HDL for Xilinx FPGA technology Input/Output Format: - Desired input/output format is Binary Testbench: - Testbench required for the Verilog code Ideal Skills and Experience: - Proficiency in Verilog HDL - Experience in BCD multiplier development - Expertise in Xilinx FPGA technology - Familiarity with Binary input/output format - Ability to create a testbench for Verilog code Goals: - Develop a functional BCD multiplier using Verilog HDL - Ensure the Verilog code passes the testbench - Optimize the design for Xilinx FPGA technology.
We want a software developer for CIJ Printer using Xilinx FPGA and stm32f429 as a processor.
Hello! I am looking for an experienced Electronics Engineer with a strong background in Xilinx ISE and a good report writing skill. The job duration is a short-term period that is less than 1 month. Expert level programming knowledge is required as well as technical document assistance. If this job opportunity is of interest, please do not hesitate to reach out! I look forward to hearing from you. The task is to Simulate a design with the aid of a “graphical testbench” (also known as a “Test Bench Waveform” file), using the Xilinx ISE v10.1.03 software. You must set the colour scheme of your simulation waveforms to the "Classic" colour scheme, via the ‘Edit’ → ‘Preferences...’ → ‘ISE Simulator (ISim)...
The main task would be initiating ways to create an ethernet communication through xilinx software for zcu216 board. ex:- PS and PL based ethernet communication, use of LWIP etc etc. We need to check the communication of signals to and from fpga board. At the end we have to create a loopback , to acquire and generate signals in a loop method. Further info in detail will be provided to review the task.
Strong skills on Embedded C/C++ · Should have knowledge in HMI based GUI development with various HD icons, sliders, graphs and drop down menus · Hands-on experience on various microcontrollers AVR/PIC/ARM/STM32F4/Xilinx XC7Z020 · IDE experiences on AVR Studio/ MPLAB/Keil IDE · Peripherals like - UART/SPI/I2C/ADC/PWM FPGA interfacing includes C Code for: ADC IC with SPI interface. DAC IC with SPI interface. 12 Bit Parallel Data interface with DAC IC. 8 Bit Parallel Data interface with DAC IC for sine wave generation. 10 PWM channel interface. SDRAM interface. SD Card Interface. USB interface RS232 Interface Current Steering DAC interface interaction experience on FPGA Able to prepare and implement the Pre-production...
Implement SCMA on PFGA by using Matlab
We are Hiring Technical expert (Xilinx Vivado) Position: Academic Technical expert Freelancer Experience: 2+ years Qualification: Masters or Doctorate in Electronics & Communication Engineering Skills Required: Turbo Decoder VLSI Xilinx Vivado FPGA Verilog Machine learning Specific area: Need a Verilog, Xilinx Vivado and Machine learning expert Time: Part-time/Freelance Job Description: Require a Freelancer, who can do coding will be done on Xilinx Vivado. Implementation will be done on FPGA using Verilog/ system Verilog language
Turbo codes are error correction codes that are widely used in communication codes exhibits high error correction capability as compared with other error correction codes. This paper proposes a Very Large...the decoder side which employs Maximum-a-Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this paper uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder Turbo encoding and decoding is done using Octave, Xilinx Vivado, Cadence system is implemented and synthesized in Application Specific Integrated Circuit (ASIC).Timing analysis has been done and GDSII file has been generated.
1)Using VHDL and the Xilinx Vivado Tools, design and implement a 4-bit ALU whose functionality is compliant with the TTL MSI 74LS381A specifications. The design must use a VHDL behavioral modeling coding style and can include concurrent and sequential statement types. Source code modules must include liberal commenting to clarify and explain function and operation your code. 2) Create a test bench VHDL module and use the Vivado Simulator to test/verify proper operation of the ALU’s functions with all input data patterns specified in the 74LS381A functional table. Recommendation: to make comparison of simulated results to those listed in the functional table easier, apply the external stimulus input patterns in the same “row” order as inputs are listed in the functi...
Hello,I am looking for guys who could integrate the AD9361 with lattice FPGA series and also port some of the codes which were made fro the xilinx FPGA into the same lattice FPGA.
The base project is Pytorch YOLOx project provided by Xilinx. We are using YOLOX Medium with a smaller input size (480×288). This reduced the complexity from ~70 to 25GFlops. The YOLOX model is trained with our labelled dataset. We'll provide project, trained checkpoint and dataset so you can prune the model and retrain. Must use structured/channel pruning The prunned model must run with the provided QAT training file: ./code/tool/ file
Hi Yadnesh. Hello. We are using the Pytorch YOLOx project provided by Xilinx and we have trained it with our labelled dataset. We will provide project, trained checkpoint and dataset so you can prune the model and retrain. Accuracy loss < 3%. Outcome of the project will be the retrained Pytorch checkpoint and pruned model file. This will be first task to see how we work together. Do you have experience with Pytorch pruning?
Hi Rachid B. Hello. We are using the Pytorch YOLOx project provided by Xilinx and we have trained it with our labelled dataset. We will provide project, trained checkpoint and dataset so you can prune the model and retrain. Accuracy loss < 3%. Outcome of the project will be the retrained Pytorch checkpoint and pruned model file. This will be first task to see how we work together. Do you have experience with Pytorch pruning?
Hi Janvi C. We are using the Pytorch YOLOx project provided by Xilinx and we have trained it with our labelled dataset. We will provide project, trained checkpoint and dataset so you can prune the model and retrain. Accuracy loss < 3%. Outcome of the project will be the retrained Pytorch checkpoint and pruned model file. This will be first task to see how we work together. Do you have experience with Pytorch pruning?
Hi Ahmed H. Hello. We are using the Pytorch YOLOx project provided by Xilinx and we have trained it with our labelled dataset. We will provide project, trained checkpoint and dataset so you can prune the model and retrain. Accuracy loss < 3%. Outcome of the project will be the retrained Pytorch checkpoint and pruned model file. This will be first task to see how we work together. Do you have experience with Pytorch pruning?
Hi Yekaterina V. We are using the Pytorch YOLOx project provided by Xilinx and we have trained it with our labelled dataset. We will provide project, trained checkpoint and dataset so you can prune the model and retrain. Accuracy loss < 3%. Outcome of the project will be the retrained Pytorch checkpoint and pruned model file. This will be first task to see how we work together. Do you have experience with Pytorch pruning?
Hi Mikhail A. We are using the Pytorch YOLOx project provided by Xilinx and we have trained it with our labelled dataset. We will provide project, trained checkpoint and dataset so you can prune the model and retrain. Accuracy loss < 3%. Outcome of the project will be the retrained Pytorch checkpoint and pruned model file. This will be first task to see how we work together. Do you have experience with Pytorch pruning?
I need to use Xilinx IIC IP on Artix board as a master, I used it in master mode and it didn't work well (The generated signal seems to be random) I tried the IP on Zynq platform and it worked well, but on Artix it beahves inproperly! I need someone to get it up and running on my chip.
Objectives of this project are Benchmarking speed, ROM, and RAM usage of software implementations of Simon and Speck's ciphers using C++ and XILINX to improve the performance of SIMON and SPECK on ASICs, FPGAs, microcontrollers, and microprocessors. - Memory benchmarking via C code - Slice count benchmarking via FPGA - Gate equivalent benchmarking via ASIC Implementation
Objectives of this project are Benchmarking speed, ROM, and RAM usage of software implementations of Simon and Speck's ciphers using C++ and XILINX to improve the performance of SIMON and SPECK on ASICs, FPGAs, microcontrollers, and microprocessors. - Memory benchmarking via C code - Slice count benchmarking via FPGA - Gate equivalent benchmarking via ASIC Implementation
Instruction Decoder and ALU Control In this lab, students are expected to implement an instruction decoder and an ALU control unit using VHDL in the Xilinx software. The purpose of the instruction decoder is to generate proper control signals based on the Opcode of an instruction fetched from the instruction memory. The purpose of the ALU control is to set the proper ALU control signal based on the Funct field of an instruction and the ALUOp signal from the instruction decoder.
Our aim with this task is to have a working ethernet stack on which we can evaluate the performance of the Zynq + GEM (Gigabit Ethernet MAC) + FreeRTOS TCP. The task is as follows: Prerequisites: 1. You must have a Zynq 7000 series development board with an ethernet port. 2. You must have Xilinx Vitis / Vivado tools installed. 3. All code on the Zynq should be in the C language. Overview: 1. Create a Vitis project for a Zynq 7000 device and a Vivado project that supports ethernet on your hardware. 2. Ensure the project runs FreeRTOS 3. Download FreeRTOS PlusTCP 4. Configure FreeRTOS PlusTCP to bring up an ethernet connection on the Zynq and demonstrate some common functionality as detailed below: We require a demonstration that the FreeRTOS PlusTCP task can: 1. Bring up the ethe...
I am looking someone having experience with MIPI CSI-2 TX (FPGA to other device, not the MIPI-CSI2 Camera into FPGA) on Xilinx MPSoC Platform and Petalinux. Its a consultation and/or development project. Anyone having experience with MIPI-CSI2 TX with any embedded Linux (ARM or other embedded platforms) can also contact me here at Project. It is moreover embedded Linux driver development work based on MPSoC FPGA.
I want to design and implement a 6-bit division circuits for unsigned numbers using VHDL in the Xilinx software.
Implementar, simular FFT en entorno aldec , bajo la plataforma Atlys Spartan-6. Simular e implementar FFT en dicha plataforma, desarrollar código VHDL y detallar minuciosamente paso a paso, tomar captures y realizar documento de word detallando cada paso la oferta es de 90 usdt. Se cuenta con la tarjeta en físico por lo cual se ofrece conexión remota
ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform
ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform
- write Verilog code for steganography algorithm so that I can be implemented on FPGA - using Verilog Xilinx ise have to write module code & test bench where it can be implemented on Fpga
...RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · Tools – Minimum 4 years of FPGA design experience – Xilinx Vivado, Intel and/or Lattice experience including Synthesis, Place and Route. · Candidate will be responsible for programming bitfiles into FPGA on multiple FPGA platforms · Timing Analysis – At least one Timing Analysis tools – Xilinx Vivado or Synopsys Primetime or Equivalent Cadence Tool. · DFT – Candidate must demonstrate knowledge of implementing Scan chain synthesis, ATPG ( Synopsys or Mentor NOT Cadence). MEM...
The project consists in implementing a buffer delay on a 100G traffic done in an Xilinx Alveo FPGA
Hi Daniel K., I noticed your profile and would like to offer you my project. We can discuss any details over chat. I have some baremetal programming on xilinx boards
A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.
I am looking for an electrical engineer who can work on FPGA TEST Board design. The project is to design FPGA TEST Board for XC7VX690T-2FFG1157I chip. We need power supply connectors as Banana jack and JTAG, UART, and SPI flash, and other decoupling capacitors and resistors. We just need simple workable Sch and PCB design wit optimal design. The candidate should have rich experience in FPGA PCB design using Altium.
I have a Xilinx KV260 board. Would like to develop a small robot project based on Vitis AI or PYNQ libraries. Need some simple documentation for education purposes. Be able to communicate.
I want the project to be done on Xilinx using Verilog/VHDL where 64bit binary counter using prescaled block can be created.
Hi, I need to create a Xilinx Petalinux project with a custom driver to control a led in Ultra96v2 board. I just need to be able to turn/off a led in Petalinux using a driver.
...acceptance of work and start of project. 2. Begin by adding PCIe BAR read logic for BAR 0 & 1. Including code snippet to do this and verification at client end on the Screamer board. The design will be able to read some predefined values via BAR reads. This will also include bring up of AC701 if required to debug hardware at my end. Beginning with work based on simulation results and documentation from Xilinx. Will try to provide this before the holiday period outlined below but can't be guaranteed. 3. Translate the driver source code header file with its comments into HDL that responds based on the comments in that file. Integrate this into PCI leech. Provide code snippet. 4. Final code and documentation hand off, address any outstanding issues. Project will begin with...
...mathematical algorithm to implement each step and phase which Comply with VIVADO HLS. Compare the result with the most recent references.(Analysis) the cloud computing environment is as you want ( Amazon , cloud Hardware ( EC2 F1) ) . It should tset the code in C++ and VHDL then compare them with Accuracy and time Vivado is belong to Xilinx and I do not need any implemantation so you can choos any chip or just do the test case the focus on simulation. The Xilinx Vivado HLS tool is one of the available high-level synthesis tools in the market. The main idea behind Vivado HLS is transforming a language specification design,into an RTL designed by converting it into Verilog or VHDL to accelerate and optimize implementation of algorithms for FPGA boards. ...
Please do NOT bid if you do not have the following experience This project requires an Experienced Embedded Programmer. 1. Prior experience in writing Interrupt Service Routines in Linux is a must 2. Prior experience with YOCTO is a must 3. Prior experience with Xilinx xDMA is a must 4. Prior experience with PCIe Interface is needed. 5. Familiarity with RISC-V architecture is a plus.
