Data acquisition

$250-750 USD

Completed

Posted

about 8 years ago

$250-750 USD

Paid on delivery

Finding maximum value by using convolution algorithm. input signal : 14-bit ADC, general input signal shape : 100ns rise time, 2us fall time There's no period. input signal is occurred randomly. Please use Xilinx ISE 14.7 tool.

Verilog / VHDL

Project ID: 10345294

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Awarded to:

@ahmedmohamed85

Dear sir I have more than 9 years experience in digital design using fpga please check my profile also please message me so that we can discuss

$780 USD in 10 days

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수원, Korea, Republic of

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Data acquisition

$250-750 USD

$250-750 USD

About the project

Looking to make some money?

Benefits of bidding on Freelancer

About the client

Client Verification

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