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    2,000 verilog ams jobs found, pricing in USD
    Verilog project with documentation. - open to bidding Ended

    Code in verilog, making Infrared communication between devices. Will provide project outline in pdf upon request. Project has to be done in Quartus.

    Arduino C Programming C++ Programming Circuit Design Electronics
    $109 (Avg Bid)
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    Zend AMS Project Ended

    Hello, We are looking for some one who can work on zend. As we want to changes layout of website inner page & sandbox form need to be align. Below is our website details: Desktop - Mobile - m.advancemedicalsystems.com. For more detail please contact me. Thanks Mohammad Shoeb

    PHP Software Architecture
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    Project for rohi1710rohi1710 Ended

    Hi rohi1710rohi1710, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I need to help in writing Verilog code for an FPGA or CPLD which will take an SPI type of data and to interface to 2 16 Bits D/A converters. SPI data basically converts to analog voltage. Can you Xilinx, Altera. the D/A's will need to be specified by the coder after review of current design. The D/A must output +/- 10V signals. The deliverables will be Verilog code only, and the manufacturer part number for the FPGA and DAC devices. There is no need to design any of the electronics. The reference schematic will be used for you to see how these components will work together.

    Engineering FPGA Translation Verilog / VHDL
    $100 (Avg Bid)
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    Write IR transmitter/decoder modules. Ended

    Code in verilog, making Infrared communication between devices. Will provide project outline in pdf upon request. Project has to be done in Quartus. 2 days deadline.

    Electronics Verilog / VHDL
    $27 (Avg Bid)
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    9 bids
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    Verilog project with documentation. Ended

    Code in verilog, making Infrared communication between devices. Will provide project outline in pdf upon request. Project has to be done in Quartus.

    Arduino C Programming C++ Programming Circuit Design Electronics
    $25 - $25
    $25 - $25
    0 bids
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    Project for SANGITAR Ended

    Hi SANGITAR, I noticed your profile and would like to offer you my project. We can discuss any details over chat.I need to help in writing Verilog code for an FPGA or CPLD which will take an SPI type of data and to interface to 2 16 Bits D/A converters. SPI data basically converts to analog voltage. Can you Xilinx, Altera. the D/A's will need to be specified by the coder after review of current design. The D/A must output +/- 10V signals.

    Electronics Engineering FPGA PHP Verilog / VHDL
    $100 (Avg Bid)
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    Project for oharwot Ended

    Hi oharwot, I noticed your profile and would like to offer you my project. We can discuss any details over chat. I need a coder who can write in Verilog code for an FPGA or CPLD which will take an SPI type of data and to interface to 2 16 Bits D/A converters. SPI data basically converts to analog voltage. You can use Xilinx or Altera. the D/A's will need to be specified by the coder after review of current design. The D/A's must output +/- 10V signals.

    FPGA Microcontroller PCB Layout Software Architecture Verilog / VHDL
    $100 (Avg Bid)
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    Neural Network, Altera DE1-Soc FPGA design, Hardware speed up Ended

    Test 400 sample of data using Neural Network algorithm to speed up hardware of FPGA in Altera Board DE1-SOC. The language is verilog and C. The C code will run on Linux system installed in the Board, this is the interface to save all the data into SDRAM. Verilog will control the hardware speed up, it will read data from the SDRAM then process it using any type of Hardware provided in the Board, then write back to SDRAM.

    C Programming Embedded Software Engineering Software Architecture Software Testing
    $277 (Avg Bid)
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    Write some software Ended

    I need you to develop some software for me. I would like this software to be developed for Windows . I need a code which is written in verilog to display a 24 hour clock on 6 of the seven segment displays (hh,mm,ss). I'm using the de2-115 board, cyclone iv e family, ep4ce115f29c7 device. I need the code to be simple and easy to understand and also require comments.

    Graphic Design PHP Website Design
    $34 (Avg Bid)
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    Verilog code for a algorithm Ended

    contact me for more details

    Electronics Verilog / VHDL
    $18 - $152
    $18 - $152
    0 bids
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    verilog project with asm Ended

    For a verilog project, which includes also asm of this, i need freelancers. contact me via chatbox.

    Algorithm Digital Design Verilog / VHDL
    $24 (Avg Bid)
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    Part 1: (Repost) Typeset into LaTeX a set of French articles by Grothendieck Ended

    See the attached PDF file that contains a description of the articles. CIick on the outlined boxes surrounding the titles. This should cause your browser to open the original source PDF file from the internet. The project contains a total of 63 scanned bid should reflect that. Please try... Also usepackage[french]{babel} to handle French hyphenation patters. I would suggest starting off the document with: documentclass{amsart} For commutative diagrams with arrows and labeled arrows use the xypic LaTeX package. I will help you as you work on it by answering any questions you have. See for documentation about AMS styles and documentclasses. Your own TeX distribution should already have this builtin.

    LaTeX Mathematics
    $104 (Avg Bid)
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    SEO 9 Sites - 0516-LMD-HIM-MM-AMR-AMS-HEUC-BABA-TFC-BAKH Ended

    On Site and Offsite SEO optimization of 9 sites - 10 keywords eachsite - 5 Articles per site (total 45 articles) - 25 High-Quality links per website from USA based (.edu, .gov, .com only) sites PR 5 and higher only on related context sites only. - 250 links for each site on classifieds, forums, social and related pr2-5 2.0 sites Must provide reports, copies of articles and verification of links. Links must be permanent

    Classifieds Posting Forum Posting Link Building SEO
    $162 (Avg Bid)
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    33 bids
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    Write some software Ended

    I need you to develop some software for me. I would like this software to be developed for Windows . Verilog/VHDL code for winograd convolution algorithm and applying that algorithm to Discrete Cosine Transform.

    Graphic Design PHP Website Design
    $18 - $152
    $18 - $152
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    Sobel Edge Detection using Verilog in Altera DE1 Ended

    By using the DE1_D5M camera module, when an image is captured, by turning a switch, the image will be converted to a sobel edge-detected image. Altera DE1 board is used in this project.

    FPGA Verilog / VHDL
    $154 (Avg Bid)
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    6 bids
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    provide a verilog model with working testbench Ended

    It is a verilog project. At first two images image filter and sample image have to be convolved by Laplacian filter. After that two convolved result will be convolved with each other and after that maxpooling have to be done to get the peaks. Finish within this sunday midnight.

    Circuit Design Electrical Engineering FPGA Software Architecture Verilog / VHDL
    $152 (Avg Bid)
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    verilog project with working testbench Ended

    It is a verilog project. At first two images image filter and sample image have to be convolved by Laplacian filter. After that two convolved result will be convolved with each other and after that maxpooling have to be done to get the peaks. Here "A" is the sample filter and "doc3" is the sample image ~tinoosh/cmpe650/hw/finalproject/ ~tinoosh/cmpe650/hw/finalproject/files/ Finish within this sunday midnight.

    Digital Design Electrical Engineering FPGA Verilog / VHDL
    $423 (Avg Bid)
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    single precision floating point multiplier using booths algo implementable on virtex 7 fpga xilinxs(verilog) Ended

    single precision floating point multiplier using booths algo implementable on virtex 7 fpga xilinxs ...need it urgently

    Verilog / VHDL
    $18 (Avg Bid)
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    3 bids
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    verilog project Ended

    i need the system in the uploaded files built

    Verilog / VHDL
    $10 - $30
    $10 - $30
    0 bids
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    fuzzy logic controller coding in verilog/vhdl and implement in FPGA board and test for DC motor speed control Ended

    i want to develop a fuzzy logic controller in fpga for dc motor speed conrol code should be written in verilog/vhdl or matlab system generator can also be used.

    FPGA Matlab and Mathematica Microcontroller Verilog / VHDL
    $253 (Avg Bid)
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    verilog simulation of algo Ended

    verilog code simulation and other requirements

    FPGA Verilog / VHDL
    $16 (Avg Bid)
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    11 bids
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    Verilog code and testbench Ended

    i need someone to make a 32 bit divider. i will send the exact problem once i accept someone for this task. thank you.

    Digital Design Engineering Verilog / VHDL
    $42 (Avg Bid)
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    Write some Software Ended

    For the ASM machine given in Hw#6: 1) Define the control signals necessary to control the parts of your data path. Clearly state the role of each signal. 2) Using Verilog and Quartus simulator, simulate the control unit, register file (RF) and the ALU. Due to the time limitation we will not simulate the instruction memory nor the data memory. But you are required to show contents of Program counter (PC) at each stage. 3) Your program should accept the assembled instructions one instruction at a time and simulate the action of the control unit to generate the control signals and show their effect on the PC, ALU and the registers in the RF. (hw6 sol is is attached ) -want the sol ASAP

    PHP Software Architecture
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    Bus Function Model (verilog coding) Ended

    I want to have BFM example verilog codes. for example ,PCI, PCIe, USB3.0, USB2.0,USB1.1, Sata3.0,Sata2.0,Sata1.0 You should have a choice of one of them or, you may suggest another BFM. BFM have to have a testbench to include main function test cases, and assertion fail statements.

    Verilog / VHDL
    $50 (Avg Bid)
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    ALU designe using Magic Ended

    The project needs only magic vlsi It does not need verilog If you gave me a good price Flexible date after two days I want project 1. I want a report 2. I want to make clear that the work of the student and simple 3. I want in the end a small problem in the project does not work because the project work that Dr. if 100% of the project work there will be a discussion and I do not want it If you gave me a good price Let's start 4- the design in the magic the hight must be 100 5- vdd is up and ground is down

    Circuit Design Electrical Engineering Electronics Microcontroller
    $279 (Avg Bid)
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    Design and implementation of motion estimation block in verilog according with the MPEG2 standard Ended

    Design a motion estimation block in Verilog according with the MPEG2 standar in order to compress a video signal resolution 640x480 and should have the performance to make video streaming. The input images will be in the RGB color space.

    C Programming FPGA Verilog / VHDL
    $188 (Avg Bid)
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    Draw the state diagram of the machine described by the Verilog model and verify Ended

    ...verify verilog problems 5.47, 5.48, 5.52, 5.58 5.47) Write a Verilog model of a synchronous finite state machine whose output is the sequence 0, 2, 4, 6, 8 10, 12, 14, 0 . . . . The machine is controlled by a single input, Run, so that counting occurs while Run is asserted, suspends while Run is de-asserted, and resumes the count when Run is re-asserted. Clearly state any assumptions that you make. 5.48 )Write a Verilog model of the Mealy FSM described by the state diagram in Fig. P5.48. Develop a test bench and demonstrate that the machine state transitions and output correspond to its state diagram. FIGURE P5.48 note: this figure is on the file a b d c 0 /1 1/0 1/1 0/0 0/0 1/1 0/1 1/0 5.52) Draw the state diagram of the machine descr...

    Verilog / VHDL
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    NEURALNETWORK verilog vhdl Ended

    Looking for expert in verilog/vhdl

    Verilog / VHDL
    $585 (Avg Bid)
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    Translate Verilog Project -> VHDL Ended

    I would like to translate a project written in VERILOG into VHDL. The project consist in reading the ambient temperature using the Nexys4 DDR board and display it on monitor using VGA. The communication between the board and sensor uses I2C protocol. The task would be just to rewrite 2 verilog files into vhdl, synthesis and implement them using xilinx vivado

    Verilog / VHDL
    $45 (Avg Bid)
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    Read the ambient temperature using NEXYS4 DDR and display it on monitor using vga Ended

    The project: Read the temperature from the FPGA Nexys4 DDR board using the incorporated temperature sensor( ADT7420) .Use in the implementation the I2C protocol. Output the temperature to the monitor using vga connection. I have a project model written in Verilog as a support if you want. Language constraints: VHDL. The project will be runned in Xilinx Vivado.

    Electrical Engineering FPGA Verilog / VHDL
    $198 (Avg Bid)
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    verily implemented micro-controller Ended

    Develop a Verilog module that implements the micro-controller

    Verilog / VHDL
    $88 (Avg Bid)
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    Designing Simple CPU in verilog Ended

    Hello Free Lancers. I need the CPU in xilinx. please look into the file which i have attached and i need the job to be done.

    PHP Software Architecture Verilog / VHDL
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    An object tracking architecture using Verilog Ended

    (only need stimulation, no need implement on FPGA, just using verilog code to get the tracking result, may be like showing coordinate in graph.) -A yuv video sequence with static background is being read and store as base hexadecimal in a .txt file by using matlab. Then using verilog code to perform following: -Load the .txt file in a memory module -Want to perform background subtraction to get the moving object -Track the moving object with kalman filter - display the result

    Verilog / VHDL
    $132 (Avg Bid)
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    Code conversion from MATLAB to Verilog Ended

    I have a couple of image processing algorithms in MATLAB. I need someone to convert it to Verilog and add a testbench (with proper comments so that I can understand the code). This is a very small project, but can give a maximum of 5 days for the job. Willing to spend not more than $50.

    Electronics FPGA Matlab and Mathematica Verilog / VHDL
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    Wowza Module Development Ended

    I need custom modules for Wowza to pull rtmp streams from AMS (Adobe Media Server) to be dynamically re-streamed in Wowza. I need development for the following: WOWZA live stream broadcast address: rtmp:// WOWZA live stream http play address: Use %s for Event ID, eg: WOWZA live stream rtsp play address: Use %s for Event ID, eg: rtsp:// WOWZA recorded videos http play address: Use %s for Event ID, eg: :%s/ WOWZA recorded videos rtsp play address: Use %s for Event ID, eg: rtsp://:%s WOWZA recorded videos rtmp play address: rtmp:// Please only bid if you have created Wowza modules.

    Java
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    Verilog CW Transmitter Radio Ended

    Using the fpga i want to produce an AM transmitter signal using a numerical oscillator at lower frequency AM signal. Using the Delta sigma modular approach(Delta sigma converter).

    Digital Design Verilog / VHDL
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    DE2-70 project board LCD module problem Ended

    I am currently doing a project using the altera DE2-70 project board and i do not know how to use the LCD module to display my output. I am requesting to develope a verilog HDL code for interfacing with the LCD module.

    Verilog / VHDL
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    Turn XML into beautiful graphics for printing! Ended

    We are a mature UK-based developer, specialists in the public transport domain. We provide services across the UK. Currently we are developing a cloud based Asset Management System and are in need of a team of two developers who can assist us in the development of an independent graphics module that will link into this AMS. While predominately web-based, the project may also require the use of server-side Windows services, console applications and scheduled tasks, so familiarity with the full Microsoft/.NET stack is important. As part of this project you will be required to extract data from XML sources and synchronise with SQL Server databases, so experience with data manipulation and specifically working with XML files is required. The project would involve working in the p...

    AngularJS ASP HTML5 JavaScript SQL
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    ALU design magic vlsi & verilog Ended

    ALU Design as l attached to you

    Circuit Design Electronics Engineering
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    Project for raulbehl Verilog Ended

    Design a full display unit and CUP mapping

    Verilog / VHDL
    $250 (Avg Bid)
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    "DMA controller modelling for application- specific array of processors along with FSM. Ended

    I just need the simple word documentation of 45 to 50 pages for the above title. The document should have its contents which should also include description about Verilog, like in the way of understanding Verilog i need simple examples like a simple digital or arudino clock. Then i need an implementation of a simple FSM which i already have the code. Then about the DMA.

    Report Writing Verilog / VHDL
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    High Performance SoC Modeling with Verilator Ended

    Project is based on the VERILATOR Simulator. The manual attached to the project is the theme of project. So, follow the manual and get all the possible results and compare them. By comparing, show that Verilator has fast simulation than other simulators (Optional). Verilator converts verilog code into system C or C++. for more information, you can log onto Verilator works better in ubuntu, so project should be the done in ubuntu.

    Engineering PHP Software Architecture Software Testing UNIX
    $30 - $250
    $30 - $250
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    Verilog coding using Spartan 3E Development board Ended

    Create a digital design to turn your FPGA development board into a simple user interface. From slide switches to a PC terminal window via a serial interface

    FPGA Verilog / VHDL
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    Intra-prediction in HEVC (video processing) for FPGA in Verilog Ended

    Designing a HEVC Intra prediction block in Verilog for a Xilinx Nexys Video FPGA board. FPGA should take a picture as input and should give encoded/reconstructed image as output. I have MATLAB code, it needs to be converted in Verilog.

    C Programming Digital Design FPGA Matlab and Mathematica Verilog / VHDL
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    Verilog simulation of a Algo Ended

    simulation needed in verilog

    Digital Design FPGA Verilog / VHDL
    $55 (Avg Bid)
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    Verilog Implementation of Pipelined Execution of Windowed Image Computations Ended

    I would like you to implement this technical paper in Verilog that can be synthesized in hardware to obtain a resource utilization report. We could go into design details if you would like to. Thanks - Aswin

    FPGA Perl Verilog / VHDL
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    Convert WP Template to a Website & Integrations Ended

    - Template Install & Customization Install WordPress Template and help with basic customization: change color, install images art and images will be provided accordingly. Configure features such as the newsfeed, links to and other generalities. Configure a "become a member" box, include a form to payment. - Insta...Install Shopify and APPS Embedded Shopify and APP into the website for the "STORE" tap - Integrations & Embedded: Salesforce and Livestream Salesforce API for all data input coming from the website to be stored appropriately in Salesforce, from all data entry points. Embedded Livestream - Third Party API, AMS Integration Install and Configure API from third party for a white label solution. Send data coming from the &...

    HTML PSD to HTML Salesforce App Development Shopify Website Design
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    Verilog Project 4 Ended

    It is a verilog project.

    Verilog / VHDL
    $56 (Avg Bid)
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    Find me a Manufacturer Ended

    ...devices and I/O ports (DDR3, SATA, HDMI, DVI, USB2, PCIe, UART, I2C) • Experienced with Analog/Digital Design, software/hardware architecture, embedded firmware, board level debug, design, system level integration, hardware design such as implementing hardware circuit blocks in analog and digital, System On Chip, ARM processor, embedded processors, embedded system, microcontroller MCU, FPGA, Verilog, VHDL, ASIC, Digital Signal Processors, MOSFET, FET, IC, electronic components and peripherals, IAR Systems • Building, soldering and modifying circuits, assembly build from Prototype board or main board, transformer, power regulator and power IC, from AC input to DC output. • Experienced in assembly, Serial Peripheral Interface, PCB fabrication, electronic componen...

    Manufacturing
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    Design of a pipelined based multiplier accumulator unit for Image processing purpose Ended

    I am doing verilog HDL for my final year project. My title is Design of a pipelined based MAC unit for image processing purpose. I have the sample coding but i cant run it as it contain error. Can someone please help me on that? This is the link for my coding. Thanks and please reply me soon. Its urgent

    FPGA Verilog / VHDL
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